1. Field of the Invention
The invention relates to the creation of test component layouts, more particularly to a computer-implemented method and system for the automated creation of test component layouts.
2. Description of the Related Art
The production of integrated circuit can be divided into an integrated circuit design phase and an integrated circuit fabrication phase. Design rules provided by the relevant manufacturing technology should be followed during the design phase. However, in view of factors, such as actual operating environment and know-how, unique to each semiconductor manufacturer, even for identical fabrication technology, such as 0.15-micron fabrication technology, each semiconductor manufacturer generally requires a distinct set of design rules that should be followed during the integrated circuit design phase.
Semiconductor manufacturers must perform component characteristic analysis for different test components, such as MOS and CMOS transistors, etc., to determine design conditions for different fabrication technologies. To this end, the semiconductor manufacturer must first prepare test component layouts before proceeding with test component fabrication according to the layouts for performing component characteristic analysis. In order to increase the accuracy of component characteristic analysis, test component layouts having different sizes of working shapes and/or different distances among the working shapes must be prepared. For example, in a MOS transistor, the length of the gate electrode, the sizes of the contacts of the source and drain electrodes, the distance between the source and gate electrodes, the distance between the gate and drain electrodes, etc., may vary for different test components.
Computer-aided tools for computer-assisted drawing of individual test component layouts are known in the art. However, layout preparation using the known computer-aided tools is tedious, inefficient and prone to human error when applied to the preparation of test component layouts for different fabrication technologies. In addition, no means is provided to filter out these errors during the preparation of the test component layouts. Thus, there is no doubt that the conventional method is a very heavy burden to semiconductor manufacturers. Besides, whenever there is a new development in fabrication technology, semiconductor manufacturers are forced to prepare new layouts to perform component characteristic analysis for different sizes of test components. These tasks require a lot of manpower and time to complete. Not only is the manufacturing cost increased, any delay in design rule throughput will place the semiconductor manufacturer at a disadvantage with other manufacturers and can result in loss of ability to compete in the market.
In summary, how preparation of test component layouts for fabrication can be shortened is always a major concern of all semiconductor manufacturers. It is noted that, for the same type of test component, the layouts thereof for different fabrication technologies vary primarily in the dimensions of the working shapes. Therefore, this invention aims to automate the conventional tedious method of preparing new test component layouts by using resources available from previous layouts, which may be for older fabrication technologies. The invention not only reduces human error to a minimum, but also provides an excellent control environment to reduce manufacturing cost and time.